The phase lock loop is commonly used in digital circuitry to synchronize clock signals. Its application includes, for example, anything requiring clock synchronization or clock synthesis, such as radar applications and telecommunications. Continuing advances in technology have resulted in an increase in the operating speed of electrical devices. Unfortunately, the speed of phase/frequency detectors ("PFDs") in the phase lock loop has not increased at a pace sufficient to keep up with technology.
Current PFDs incorporate multiple logic devices that cause significant logic delays and limit the PFD's maximum operating frequency. If the PFD's maximum operating frequency is less than that of the voltage controlled oscillator ("VCO"), the phase lock loop may fail to function properly. For example, it may enter a condition known as VCO runaway.
One technique to incorporate a frequency limited PFD is to add additional hardware logic and/or software to detect and correct such failure situations. This increases costs and may limit performance.
Another technique to incorporate frequency limited PFD's in higher frequency circuitry reduces the clock signal frequency prior to presentation to the PFD. This results in increased overhead due to additional elements placed in the phase lock loop, and introduces more error sources and potential for device failure.